The subject system and method are generally directed to memory controllers having measures for carrying out ongoing maintenance refresh operations for a memory device in optimized manner More specifically, the subject system and method provide for a memory controller that is executable to adaptively actuate ongoing refresh operations so as to minimize disruption to operational data transactions for accessing the memory device. The subject system and method preferably carry out such adaptively optimized refresh of memory while preserving compliance with applicable memory maintenance requirements.
Memory controllers are well known in the art. They are implemented as digital circuits dedicated to controlling/managing the flow of data written to and read from one or more memory devices, and to preserve the same by periodically refreshing the memory as needed. They may be suitably formed as separate devices or integrated with a central processing unit or other main controller, and serve the memory storage and access needs of various control or user application ‘master’ operations processed thereby. Memory controllers implement the logic necessary to read from and write to various types of solid state memory devices, examples of which include dynamic random access memory (DRAM), as well as electrically programmable types of non-volatile memory such as flash memory, and the like.
Refresh operations essentially replenish the charge stored in the memory cells of a solid state memory device. While not all solid state memory devices require periodic refresh, many memory devices configured for high speed access, such as DRAM devices, require sufficiently consistent level of periodic refresh for data stored in its memory cells to be adequately preserved. The capacitive storage cells typically employed in various memory devices do not hold electric charge indefinitely, and tend to lose their charge over time. Unless refreshed on average at least once within a certain maximum interval of time, a storage cell may be subject to corruption for that reason. Industry standards such as those established by the Joint Electron Device Engineering Council (JEDEC) for semiconductor memory circuits and devices, for example, enforce this requirement through an average periodic refresh interval time parameter, commonly referred to under JEDEC standards as tREFI. This parameter derives from a refresh time window parameter, commonly referred to under JEDEC standards as tREFW, and a minimum number of refreshes for all available banks (a predetermined array of memory cells) of the memory device required within each rolling period of time equaling such window in duration.
Automatic refresh is carried out as a periodic yet ongoing maintenance requirement, and therefore comes at operational costs. The costs of refresh typically include such performance implications as the need to close a page (typically defined as a row of memory cells of a particular bank) before it may be refreshed. If a particular page of memory has been opened (activated) for execution of a memory access transaction, the page must be closed (made idle) before refresh may occur. During refresh, a page remains closed, such that reading and writing to that part of memory is disabled.
Each refresh cycle thus entails a cost in terms of time latency. That is, from the time a refresh command issues for a row of memory cells, some minimum time delay must transpire in practice before that same row of memory cells may be accessed again (as denoted, for example, by the parameter tRFC commonly referred to under JEDEC as the refresh recovery time). In addition to this recovery time, delay components are also incurred: from the time data is actually stopped to when a page is actually closed; from the time the page is closed to when a refresh command issues; and, from the time the page is opened to when data access gets underway. The sum of all such delays amounts to a period where the given part of memory essentially remains offline in terms of data accessing operation, potentially lengthening the total operational time required for transfer of read/write data back and forth from memory.
Tasks like closing and reopening a page come also with power implications. Repeatedly executing such tasks in carrying out refresh commands, for example, often results in large enough current draws to require special handling. This may pose undue risk of corruptive failure.
Refresh operations may therefore consume considerable overhead and measurably encumber memory performance in a given application. In other words, refresh makes for a direct hit on bandwidth utilization of a memory device.
To minimize the disruptive effects of refresh on memory utilization, system developers have turned with limited success to systematic approaches like providing the option of not only a blanket refresh of the entire device, but also a more granular refresh of a given memory device on a per-bank basis. Although the approach permits those banks not targeted by a pending refresh command to continue being accessed for read and write commands, it requires a considerably greater number of refresh commands to cover all banks of the memory device. Depending on the application, this may inject needless delay, as the collective overhead time costs for issuing the added refresh commands may become prohibitively high.
There is therefore a need for a memory controller system and method capable of automatically actuating refresh operations on a memory device, while preserving compliance with applicable operational requirements. There is also a need for a memory controller system and method which provides adaptive refresh of different portions of a memory device to mitigate the costs of refresh and optimize the efficiency and flexibility of memory utilization. There is a need, moreover, for a memory controller system and method provides for such adaptive refresh to be carried out at multiple selective levels of granularity.